Advanced Hardware and Computing

1. What is "ECC memory"?

• A. Extra Cache Controller memory
• B. Error-Correcting Code memory that detects and corrects single-bit memory errors ✓
• C. Extended Cache Capacity memory
• D. Encrypted Cache Controller memory

💡 ECC memory detects and corrects single-bit errors automatically, critical for servers and workstations where data integrity is paramount.

2. What is the "von Neumann bottleneck"?

• A. A CPU speed limitation
• B. The limitation caused by the shared bus between CPU and memory slowing data transfer ✓
• C. A type of memory error
• D. A power limitation

💡 The von Neumann bottleneck describes how the single bus connecting CPU and memory limits performance as CPU speeds outpace memory bandwidth.

3. What is "dark silicon"?

• A. Black-colored silicon chips
• B. The portion of a chip that must be powered off at any given time due to power and thermal constraints ✓
• C. A type of defective chip
• D. A new semiconductor material

💡 Dark silicon refers to transistors that must remain powered off to prevent overheating — a fundamental challenge as chips shrink further.

4. What is "NUMA" in computer architecture?

• A. Non-Uniform Memory Access — where memory access time depends on memory location relative to the processor ✓
• B. New Unified Memory Architecture
• C. Network Unified Memory Access
• D. Non-Unified Memory Allocation

💡 NUMA architecture has multiple memory banks where access time depends on which processor is accessing which memory bank.

5. What is "out-of-order execution" in CPUs?

• A. Executing instructions in a random order
• B. Executing instructions in a different order than the program specifies to maximize CPU resource utilization ✓
• C. A type of branch prediction
• D. A scheduling algorithm

💡 Out-of-order execution allows CPUs to execute later instructions while waiting for earlier ones to complete, improving throughput.

6. What is "branch prediction" in CPUs?

• A. Predicting program crashes
• B. A CPU technique predicting which branch of conditional code will execute to improve pipeline efficiency ✓
• C. A type of memory management
• D. Predicting thermal throttling

💡 Branch prediction guesses which path a conditional instruction will take, loading those instructions speculatively to avoid pipeline stalls.

7. What is "photonic computing"?

• A. Computing using photographs
• B. Using photons (light) instead of electrons for computation and data transfer ✓
• C. A type of quantum computing
• D. A type of display technology

💡 Photonic computing uses light instead of electrical signals for computation and data transfer, offering potential for extreme speeds and efficiency.

8. What is the difference between RISC and CISC architectures?

• A. No difference
• B. RISC uses fewer, simpler instructions; CISC uses more complex instructions ✓
• C. CISC is faster always
• D. RISC uses more power

💡 RISC (Reduced Instruction Set Computing) uses simpler, fixed-length instructions. CISC (Complex) uses variable-length, complex instructions.

9. What is "die shrink" in semiconductor manufacturing?

• A. Making chips physically larger
• B. Reducing the transistor size to fit more transistors on the same chip area ✓
• C. A type of chip cooling
• D. Removing defective chips

💡 Die shrink reduces transistor size (e.g., from 7nm to 5nm), allowing more transistors per chip for better performance and efficiency.

10. What does "TDP" stand for in processor specifications?

• A. Total Data Processing
• B. Thermal Design Power — the maximum heat a cooling solution must dissipate ✓
• C. Transistor Density Performance
• D. Total Dynamic Power

💡 TDP (Thermal Design Power) indicates the maximum heat generated by a CPU/GPU under load that the cooling system must handle.

11. What is "quantum supremacy"?

• A. Quantum computers replacing all classical computers
• B. When a quantum computer performs a specific calculation faster than any classical computer could in a reasonable time ✓
• C. A security standard
• D. A quantum networking protocol

💡 Quantum supremacy (demonstrated by Google in 2019) occurs when a quantum computer solves a problem practically impossible for classical computers.

12. What is "simultaneous multithreading" (SMT)?

• A. Running one thread at a time
• B. A CPU feature allowing multiple threads to run on a single physical core simultaneously ✓
• C. A type of multiprocessing
• D. A memory management technique

💡 SMT (Intel calls it Hyper-Threading) allows a single physical core to execute multiple threads simultaneously by sharing execution resources.

13. What is "pipelining" in CPU design?

• A. A type of memory bus
• B. Breaking instruction execution into stages processed simultaneously for different instructions ✓
• C. A type of cache
• D. A power management technique

💡 Pipelining overlaps execution of multiple instructions by breaking them into stages (fetch, decode, execute, write-back) processed simultaneously.

14. What is "stochastic computing"?

• A. Random number generation
• B. A computing paradigm representing data as random bit streams and performing operations with simple logic gates ✓
• C. A type of error correction
• D. A machine learning technique

💡 Stochastic computing represents values as probabilities in random bit streams, enabling complex computations with simple hardware at the cost of precision.

15. What is "chiplet" architecture in modern processors?

• A. A very small chip
• B. Combining multiple smaller chips (chiplets) on one package instead of one monolithic die ✓
• C. A type of cache
• D. A type of GPU

💡 Chiplet architecture assembles multiple smaller specialized chips into one package, improving yields and allowing mixing of different process nodes.

16. What is "speculative execution" in CPUs?

• A. Running programs speculatively
• B. A CPU optimization where instructions are executed before it is known if they are needed ✓
• C. A type of cache memory
• D. A power-saving mode

💡 Speculative execution preemptively executes instructions before confirming they are needed, improving performance. It was exploited in Spectre/Meltdown.

17. What is "FinFET" transistor technology?

• A. A type of CPU cooling
• B. A type of DRAM
• C. A 3D transistor design using fins to control current flow, enabling smaller and more efficient chips ✓
• D. A type of SSD

💡 FinFET (Fin Field-Effect Transistor) uses 3D fin-shaped gates to better control current, enabling sub-10nm chip manufacturing.

18. What is "PCIe" used for?

• A. Powering USB devices
• B. Peripheral Component Interconnect Express — high-speed interface connecting GPUs, SSDs and other components to the CPU ✓
• C. A type of RAM slot
• D. A network interface

💡 PCIe is the standard high-speed interface for connecting graphics cards, NVMe SSDs, and other high-bandwidth peripherals to the CPU.

19. What is "cache coherency" in multi-core processors?

• A. Keeping cache memory clean
• B. Ensuring all processor cores have a consistent view of shared memory ✓
• C. A type of cache eviction policy
• D. Synchronizing CPU clocks

💡 Cache coherency ensures that when one core modifies data, all other cores see the updated value, not stale cached copies.

20. What is "HBM" memory?

• A. Hard Byte Memory
• B. High Bandwidth Memory — 3D-stacked DRAM providing much higher bandwidth than traditional DRAM ✓
• C. Hierarchical Buffer Memory
• D. High-speed Block Memory

💡 HBM (High Bandwidth Memory) stacks DRAM dies vertically with a wide interface, providing extremely high memory bandwidth for GPUs and AI accelerators.